The Associate ASIC Engineer will be a key hands-on contributor, interacting with internal stakeholders and outsourced partners, to help enable Acacia’s rapidly growing and expanding product portfolio. The individual will be a member of Acacia’s ASIC team and contribute to the hardware life cycle of our products and will work within a multi-disciplinary hardware, Software, Optics, and DSP engineering organization. Responsibilities for this position consist primarily of writing and debugging simulation test cases for complex communications ASICs.
Candidate must have excellent interpersonal skills. The candidate must be self-motivated, have strong written and oral communication skills, be able to manage their time well, and be able to report on complex technical issues.
Key Essential Functions:
- Work with senior team members to define test plan and enhance simulation infrastructure
- Write simulation tests in C++/Verilog to verify design against specification
- Debug simulation failures
- Generate and analyze functional and code coverage reports.
Minimum Qualifications, Experience, Skills, Education and Certifications:
- Currently enrolled in a Bachelors or Masters degree majoring in Computer Science, Computer Engineering, or Electronic or Electrical Engineering or recent graduate.
- Knowledge of C++, Verilog, SystemVerilog
- 3.3 minimum GPA
- Good interpersonal and organizational skills
Other Desirable Skills:
- Passion about engineering
- Scripting languages such as perl, python, tcl or Make
- DSP course work a plus.
- Likes to be challenged to understand system and figure out ways to break it
- Previous internship experience